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Synplicity Enhances Synplify Pro Product to Overcome IP Integration Barriers
SUNNYVALE, Calif.----Nov. 13, 2000--
Synplicity, Inc. (Nasdaq: SYNP), a leading supplier of software
for the design and verification of semiconductors for Internet
infrastructure, today announced it has enhanced its Synplify Pro(TM)
synthesis solution to support designers integrating intellectual
property (IP) into high-density FPGAs. With this new release, the
synthesis product includes support for FPGA designs containing both
Verilog and VHDL modules, known as ``mixed-language'' designs.
Additionally, the new release offers support for IP cores whose timing
is modeled in the STAMP format, enabling improved timing performance
in designs using pre-synthesized IP. Synplicity® also announced the
Synplify Pro software supports the Xilinx Modular Design Flow.
Synplicity has improved quality of results for Xilinx Virtex-II
devices and Altera APEX20K/E families while adding new support for
devices from Actel, Lattice Semiconductor, Lucent, QuickLogic and, for
the first time, Triscend.
``Today, it has become commonplace to utilize IP in FPGAs in order
to quickly add functionality and meet stringent time to market
requirements,'' said Andy Haines, vice president of marketing for
Synplicity. ``However, integrating the modules can be tricky and time
consuming if the IP module is written in a language different from the
primary design language, or the timing of the IP module is unknown.
With today's enhancements to our Synplify Pro synthesis solution, we
believe that we have eliminated two major hurdles associated with
design reuse and have helped to ease the design of complex FPGAs.''
Mixed-Language and STAMP Support
The new Synplify Pro release offers mixed-language support, giving
designers the ability to mix Verilog and VHDL modules within a design.
Traditionally, a designer would have to manually re-implement an IP
module if it were written in a language different from the primary
language of the design. The Synplify Pro software enables
communication between the modules, eliminating the need to
re-implement the IP module. This becomes increasingly important as
programmable logic design density increases and design reuse becomes a
necessity. This mixed-language support can also benefit a team of
designers implementing complex FPGAs by allowing individual designers
to work on portions of the design in their language of choice.
The software also includes support for the STAMP modeling format,
enabling synthesis to understand timing within IP modules and
therefore better optimize its surrounding logic. STAMP is a popular
modeling format that is part of Synopsys Liberty(TM) program.
Enhancements for Xilinx Customers
The enhanced family of Synplify® products includes new quality
of results improvements for Xilinx Virtex-II FPGAs, including Dynamic
SRL support, automatic inference of Up/Down counters and support for
simultaneous read and write for BlockRAMs. With this release,
sequential shift components are automatically inferred and then
implemented as an SRL (Shift Register Lookup) table, significantly
improving performance in designs using these components.
For the first time, the Synplify Pro software includes support for
the Xilinx Modular Design Flow. Using the Synplify Pro product within
the Modular Design Flow, design teams can easily define modular
boundaries for each team member, and generate separate netlists and
constraints for each section of the design. This approach is important
for the design of very complex devices where portions of the design
must be completed incrementally.
Enhancements for Altera Customers
This new release of Synplify software includes several new quality
of results improvements for Altera's APEX20K and APEX20KE family of
devices including automatic inference of Up/Down counters,
improvements for timing optimization, mapping of cascade/carry chains,
automatic inferencing or ROMs and mapping to LPM ROMs and NativeLink
support for Unix. Together these improvements provide APEX users with
significantly faster performing devices.
Support for New Devices from Leading Vendors
For the first time, the Synplify products include support for
Triscend's A7 and E5 device families, which offer a configurable SoC
solution to address high-performance, customizable SoC applications.
Additionally, the Synplify synthesis solutions now offer support for
Actel 54SXS and eX families, Lattice SuperFAST and SuperWIDE families,
Lucent Orca4 family and QuickLogic QuickDSP family.
Pricing and Availability
The Synplify 6.1 and Synplify Pro 6.1 synthesis solutions are
available now. Pricing for the Synplify software starts at $9,000
(U.S.) and pricing for Synplify Pro software starts at $19,000 (U.S.).
Current customers on maintenance will be upgraded at no additional
cost.
About Synplicity
Synplicity, Inc. (Nasdaq: SYNP) is a leading provider of software
products that enable the rapid and effective design and verification
of semiconductors used in Internet infrastructure hardware and other
electronic devices. The company leverages its innovative logic
synthesis, physical synthesis and verification software solutions to
improve performance and shorten development time for complex
programmable logic devices, application specific integrated circuits
(ASICs) and system-on-chip (SoC) integrated circuits. Synplicity's
fast, easy-to-use, affordable products offer extremely high quality of
results, support industry-standard design languages (VHDL and Verilog)
and run on popular platforms (Windows 98/2000, Windows NT and UNIX).
The company is located at 935 Stewart Drive, Sunnyvale, Calif. 94085.
Telephone: 408/215-6000; Fax: 408/990-0290; E-Mail:
info@synplicity.com.
The specific features, functionality and release timing of any new
products or new versions of current products remains at the sole
discretion of Synplicity, Inc., and no warranty is made as to when or
if specific features, functionality or releases may occur.
Synplicity and Synplify are registered trademarks of Synplicity,
Inc. Synplify Pro is a trademark of Synplicity, Inc. All other brands
or products are the trademarks or registered trademarks of their
owners.
Contact:
Tsantes & Associates
Steve Gabriel, 408/369-1500 x27
steve@tsantes.com
or
Synplicity, Inc.
Jeff Garrison, 408/215-6000
jeff@synplicity.com
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